Add VDD_MX and VDD_CX rpmh-regulator subnodes which are used by
the VDD_MMCX regulator device. Configure these sub nodes so that
a request for VDD_CX >= minimum operating level is present any
time that VDD_MMCX is enabled.
This ensures that multimedia hardware blocks are not accidentally
reset due to VDD_MMCX being enabled when VDD_CX is not enabled.
Implement the following <child> --> <parent> supply dependencies:
pm8350c_s8_level (MMCX) --> pm8350_s5_mmcx_sup_level (MxA)
pm8350_s5_mmcx_sup_level (MxA) --> pm8350_s9_mmcx_sup_level (MxC)
pm8350_s9_mmcx_sup_level (MxC) --> pm8350c_s6_mmcx_sup_level (CX)
Note that the final MxC to CX supply dependency only propagates
the enable state of the regulator, not the voltage level. This
ensures correctness while also minimizing power consumption.
Change-Id: Ib1c7d4fa685e88d62c7e31b1e6a1ae396aed4edb
USB device failed to enumerate with USB host as USB bus aggre_noc
was not enabled related to secondary USB controller. Fix this issue
by using correct aggre_noc clock handler.
Change-Id: I8a8cc75911a37df705f6d1389b3771a6b6982f41
PCIe needs to switch between XO and pcie_*_pipe_clk based on
LPM state. Add the clocks to support this on lahaina.
Change-Id: I44efe4752d5a9d93a7fff5809b272fa4b6146f14
Add aggre_noc_pcie_0_axi_clk and aggre_noc_pcie_1_axi_clk for
the corresponding PCIe devicetree node on lahaina.
Change-Id: Ic5940f38b83b54aeb77d310b144a75e15c72b74f
Change the initial mode of all rpmh-regulator LDO devices from
low power mode (LPM) to high/normal power mode (HPM). This
avoids problems during boot up if a consumer requests a voltage
before requesting a load current as this will result in the
LDO regulator being switched to LPM. A subsequent load current
request will switch it to HPM. However, if the LDO was enabled
and sourcing more current than the LPM limit, then this brief
period can cause the voltage to drop out and lead to hardware
faults.
Change-Id: Ibecd9c439a6b382642a6131eecb92c2a50f64a05
Creating logical mappings for the secure CDSP heap memory may
cause problems with respect to speculative access, so ensure
that no logical kernel mappings are created for that region.
Change-Id: I56c23e82c1a4ba52322aa0f5a2045e482a8586ff
As the emulation platform is very slow, we may encounter watchdog
barks/bites very often. Hence, explicitly disable the device-tree
node for the watchdog driver for this platform.
Change-Id: I11e48439370efdd27c2c6cee6798fe0d22e2bd7d
Update the arch_timer frequency to 19.2 MHz, now that the device
boots up on a real hardware (instead of an emulation platform).
Leave the 96KHz still intact for emulation platforms.
Change-Id: I3745395b88d8aa9d1b0047b4eca7c85db4ec7a13
When lahaina-rumi is compiled as a separate overlay, it does
not explicitly include the definition of the &soc node. Without
the #address-cells and #size-cells specifiers, the compiler uses
default values of 2 and 1, respectively, which results in the
following warnings when compiling lahaina-rumi-overlay.dtb:
Warning (reg_format): "reg" property in
/fragment@15/__overlay__/usb_emu_phy@a720000 has invalid length (8
bytes) (#address-cells == 2, #size-cells == 1) Warning
(avoid_default_addr_size): Relying on default #address-cells value for
/fragment@15/__overlay__/usb_emu_phy@a720000
Warning (avoid_default_addr_size): Relying on default #size-cells
value for /fragment@15/__overlay__/usb_emu_phy@a720000
As the &soc node is referenced here only for the purpose of adding
a new child node, usb_emu_phy, address the warnings by explicitly
defining the {address,size}-cells values.
Change-Id: I8b5ebcd53c060eeea3c55bf9fb8e55093e7862f2
Qualcomm Technologies, Inc. (QTI) High Voltage (HV) PMIC haptics
modules can support up to 10 V voltage to drive either ERM or LRA.
It has an integrated module to support auto resonance detection
and correction for LRA actuator. It can play different vibration
effects with different pattern sources. It also has an integrated
brake module which can work in different modes to use BEMF for
quick vibration stop.
Change-Id: Id8b9fa1e4eefc7dda325e25728e59af9c1de9049
Add a secure display heap of size 164 MB for carveout memory
required to support 3 concurrent secure Video sessions.
Change-Id: I5d88df171370e7f3cc9ad723db1d2736e1bf614f
Add support for managing the PM8008I and PM8008J chips via I2C.
Replace the stub-regulator device nodes for these PMICs with
subnodes inside of the respective I2C devices. This ensures
that consumers are able to modify the physical state of these
PMIC regulators.
Change-Id: Ieb4976ecd8818c7515c2fbf61c754518215fd5bd
Add a register value mask which will specify which bits of the register
will be updated with the value. For instance, if mask is 0x11, then
only bit 0 & bit 4 will be updated with the corresponding bits of the
specified value.
Change-Id: I27471c3afee72ac99f955030ab2100f3685d46d9
OCS errors are seen due to a SMMU config mismatch
between bootloader and hlos.
Bootloader enables IO-coherency for SMMU, but hlos
has not marked the ufs device as coherent.
This causes MISMATCH_DATA_BUFFER_SIZE error.
Fix this by marking UFS device as coherent.
Change-Id: I852394aaf549652e13886210422111060a626b12
Document usage of interconnects and interconnect-names properties
for the USB controller node. This replaces the now obsolete msm_bus
bindings.
Change-Id: I4a1a2cd6a115584986bba28ba121d3fbea7cb409
