Add lahaina-usb.dtsi which defines USB controller nodes and no-op
PHY. In addition, add entries for the emulation PHY to
lahaina-rumi.dtsi with overrides to limit the USB instances to
high-speed, peripheral-only.
Change-Id: I987a18c07c5406de3c924fcf03db13a72e9ab2de
To prevent the possibility of running out of stream-matching
entries (SMEs) on the KGSL SMMU in cases where all the SMEs
are required, disable the coherent KGSL IOMMU test device.
Change-Id: I1d1cf1a4530680de91c839d22f057b807765111d
Update the board-id property to include major and minor ids as well
for the bootloader to pick the correct version of devicetree.
Change-Id: I9403d2b2fb88e55db4e68ceea9d884d507167cc7
The PIL drivers need to vote for bandwidth across DDR and
crypto subsytem, such that the secure world can perform
initialization and authorization of the firmware blobs.
Hence add a device-tree node indicating the corresponding
interconnect.
Change-Id: If5626ad20638434e39a7d4aa0f02149a72bdaf12
The QMP debugfs client is used to send test commands to the AOP over
QMP. Users can echo commands to a debugfs node and the QMP debugfs
client driver will copy those commands and send them to AOP.
Change-Id: I49fa586110cfe53886b5b5e0b1c9aa906d3d50cb
The msm_qmp driver is used to send packets to the aop. The messages
are sent over msgram owned by aop. This is a lightweight protocol that
only supports one packet in flight in any direction.
Change-Id: I3780bdb955f74a2609d870e65c58d228b9cf27cc
Add edac node with compatibility of arm,arm64-kryo-cpu-erp,
to enable error reporting capability for L1/L2 & L3 memories
on Lahaina SoC.
Change-Id: Id561334e40c0aaf04348db90df4a30252ded2432
Fix the size of the register space for the graphics SMMU,
and enable it, as well as the associated test devices.
Change-Id: I5963b9d5a5fb0ad1d55a1e2011ee1bfb5d961fee
Add the device-tree bindings documentation for Inter-Processor
Communication Controller (IPCC). This include the bindings for
the driver as well as the test-driver.
Change-Id: I8857cdbc42c9612487071c74b4bbef8f52cb4ec6
Make the LLCC device-tree node compatible with "qcom,lahaina-llcc"
so that it could be matched with the LLCC driver for Lahaiana
platform.
Change-Id: If362950496a2e9b6f073c59ed703072da741a67d
Add "qcom,llcc-lahaina" compatible property which specifically matches
the driver for Lahaina platform.
Change-Id: Iaf088ad7e90276e8b4b9a40341fd8e92e7307f47
Add the device-tree bindings that describe the device-tree
properties for the MSM ION memory manager.
Change-Id: I757dc97ebcde58a71f4358d54eacf11478e109c3
Add the initial set of devices that describe the APPS
and graphics SMMU register spaces for the Lahaina.
Change-Id: I308c55d050cd199f5a9d97fdf77319f4b77c8c30
Add the secure buffer device for Lahaina to secure memory
buffers, and protect them against unauthorized access.
Change-Id: I7b07d32bb51667e18666295a2504dd029cb22c3f
Add stub interconnect devices for aggre1_noc, aggre2_noc,
config_noc, dc_noc, gem_noc, lpass_ag_noc, mc_virt_noc,
mmss_noc, nsp_noc, system_noc, This will allow consumers to
get their path and set bandwidth constraints on them.
Change-Id: Ic2ec48af802b6d763c857482facddf4367570b24
Add the Secure Channel Manager device-tree node to
communicate with the secure world on Lahaina platform.
Change-Id: I7002f90265830131acc2fca1f93934932d56eff4
Add device-tree bindings documentation describing the
properties for the Secure Channel Communication (SCM) driver.
Change-Id: I1fa64f643a6be9281ef7b127506171948decc7be
Add interconnect device bindings. These devices can be used to
describe any RPMH and NoC based interconnect devices.
Change-Id: Iab822d4ced5aa015748ccbe464ffb616767a34c2
Update device tree bindings from snapshot tmp-f686d9f. tmp-f686d9f
is based on the Android Common Kernel, as of commit <f686d9f9fc>
(ANDROID: update abi_gki_aarch64.xml for 5.2-rc6).
Change-Id: I4271008067d7acba8a4c5753aef488feb3d37a12
Add pinctrl node with compatiability of qcom,lahaina-pinctrl,
to enable Top Level Mode Multiplexer block(TLMM) on Lahaina SoC.
Change-Id: Iac61248547061d5cb2ec42e442117f676f54ff77
Add stub clock devices for rpmh, aop, gcc, videocc, camcc, dispcc
and gpucc clock controllers on the Lahaina SoC. This allows consumers
to reference dummy clocks until full functionality is in place.
Change-Id: Idd7c45aaa301cd0688c4f7ca59ddfe3447bf996e
Add dummycc device bindings. These devices are used to reference
clock controllers and emulate clock operations.
Change-Id: Icf6464f85374d7969b24e19ae458a245125b7f88
