Commit graph

1,588 commits

Author SHA1 Message Date
qctecmdr
cf61e1e193 Merge "ARM: dts: msm: Open NOM_L1 gpu powerlevel for A660 v1" 2020-07-04 10:39:43 -07:00
qctecmdr
03f9bcd664 Merge "ARM: dts: msm: Add flags to estimate thresholds for BCL in lahaina" 2020-07-04 10:39:42 -07:00
qctecmdr
c2ef6bea52 Merge "ARM: dts: msm: Add stub interconnect devices for sdxlemur" 2020-07-04 04:29:30 -07:00
qctecmdr
c0fbc6296f Merge "ARM: dts: msm: Update RPM-SMD clock node for HOLI" 2020-07-03 22:59:54 -07:00
qctecmdr
1f59c06aec Merge "dt-bindings: Add documentation wlan platform driver" 2020-07-03 22:59:54 -07:00
qctecmdr
e0350cc1a8 Merge "ARM: dts: msm: Add rmtfs_sharedmem support for Shima" 2020-07-03 22:59:54 -07:00
qctecmdr
64bea02e81 Merge "ARM: dts: msm: Add memshare for lahaina" 2020-07-03 17:48:40 -07:00
qctecmdr
3509258440 Merge "ARM: dts: msm: Disable L1SS sleep for Lahaina" 2020-07-03 17:48:40 -07:00
qctecmdr
e49daff97c Merge "ARM: dts: msm: Include sdxlemur stub regulator" 2020-07-03 12:28:53 -07:00
qctecmdr
a6f8feba47 Merge "ARM: dts: msm: Add coreisght device tree for shima" 2020-07-03 12:28:53 -07:00
qctecmdr
a7580172cb Merge "ARM: dts: msm: Add LPASS pil node for Holi SoC" 2020-07-03 12:28:53 -07:00
Sandeep Singh
88777d15ec dt-bindings: Add documentation wlan platform driver
This change add entry of wlan platform driver for iWCN
architecture.

Change-Id: Ic89fb32a944eaefe88a568e6b998b475c7dd68ea
2020-07-03 06:28:21 -07:00
qctecmdr
aed7ab7fd4 Merge "ARM: dts: msm: Add IPCC register range" 2020-07-03 04:10:15 -07:00
qctecmdr
7372aad95a Merge "ARM: dts: msm: Enable symmetry in Lahaina led switch devices" 2020-07-03 04:10:15 -07:00
qctecmdr
c86cb7aabd Merge "ARM: dts: msm: Update clock nodes and GDSC for SHIMA" 2020-07-03 04:10:15 -07:00
qctecmdr
7d3e5e7b8b Merge "dt-bindings: mailbox: Add compatible for sdxlemur" 2020-07-03 04:10:15 -07:00
qctecmdr
07856c8719 Merge "ARM: dts: msm: Add VADC and ADC_TM nodes for holi" 2020-07-02 22:46:55 -07:00
Mohammed Mirza Mandayappurath Manzoor
026aa276ab ARM: dts: msm: Open NOM_L1 gpu powerlevel for A660 v1
Expose NOM_L1 power level for A660 v1 devices.

Change-Id: I3ca084c3c6fb24a9ffc26c33505d01c6f40b52a8
2020-07-02 10:28:38 -07:00
Hemant Kumar
bdcff7e7b9 ARM: dts: msm: Disable L1SS sleep for Lahaina
Remove the software workaround to manually manage
the phy PLL. Keep the phy PLL on all the time by
disabling L1SS sleep. This is required to prevent
PCIe link down issue upon exiting the L1SS sleep.

Change-Id: I6251f05d1ae0572b958740460606e3eeb51c59ed
2020-07-01 11:51:58 -07:00
Yogesh Lal
d1a9f63c8d ARM: dts: msm: Add LPASS pil node for Holi SoC
Add LPASS pil node for LPASS subsystem loading for Holi.

Change-Id: I254b2aa071afc74828152be2bec0dd8c7f50fb73
2020-06-30 09:21:06 +05:30
Yogesh Lal
861f194e1f ARM: dts: msm: Add scm node for Holi SoC
Enable scm node to support subsystem pil loading for Holi.

Change-Id: I750b1d87310088486fd005ad9ce4943fa3e94c4b
2020-06-30 09:20:40 +05:30
Ram Chandrasekar
9f8afd4aa7 ARM: dts: msm: Add flags to estimate thresholds for BCL in lahaina
Mention the new property qcom,pmic7-threshold for the BCL device in
lahaina, so that the software will account for the no bit shift in the
threshold register.

Change-Id: Id939e2eaa64235645cd2948dfba0fbcd3ab6bd8b
2020-06-29 11:25:32 -07:00
Ram Chandrasekar
ba262f666c dt-bindings: thermal: Add a property to account BCL threshold bit shift
Newer BCL hardware doesn't have the threshold registers bit shifted
compared to the ADC measurement register. Add a new flag
qcom,pmic7-threshold, which needs to be added for these new targets so
that the software driver will account for the bit shifting in the
threshold calculation.

Change-Id: I6bc33f14a2717e060c9d32d199df10cc269ca6f1
2020-06-29 11:25:28 -07:00
Tao,Zhang
68bcee4d37 ARM: dts: msm: Add coreisght device tree for shima
Add coresight config to device tree for shima.

Change-Id: I39fee1e3f550d09ee81bacf189a6e571a6d5c071
2020-06-29 20:20:58 +08:00
Sahitya Tummala
13939dada5 ARM: dts: msm: Add rmtfs_sharedmem support for Shima
Add shared memory support to enable the rmt_storage service
in userspace that allows other processor to access the primary
storage device to store its data.

Change-Id: I840d74076c25e1e73ba187fccce28628b8356196
2020-06-29 14:07:57 +05:30
Naveen Yadav
820c448e1f ARM: dts: msm: Add stub interconnect devices for sdxlemur
Add stub interconnect devices for system_noc, mem_noc, mc_virt
and ipa_virt. This will allow consumers to get their path and
set bandwidth constraints on them.

Change-Id: I37af153914bf86da471f220976522cc336dcdd37
2020-06-28 18:05:36 +05:30
Naveen Yadav
85ddb3e7b1 dt-bindings: interconnect: add interconnect bindings for SDXLEMUR
Add interconnect device bindings. These devices can be used to
describe any RPMH and NoC based interconnect devices.

Change-Id: Ice8cf23e6fc6251addd2976ee8acd95eb2c88c2d
2020-06-28 15:45:59 +05:30
qctecmdr
e0e90a0342 Merge "ARM: dts: qcom: Enable USB U1/U2 on Lahaina" 2020-06-26 19:54:04 -07:00
qctecmdr
fd72b4f720 Merge "ARM: dts: msm: Add dummy clock nodes for clock controllers for SDXLEMUR" 2020-06-26 19:54:04 -07:00
qctecmdr
ee6fc394e0 Merge "ARM: dts: msm: Update capacity-dmips-mhz values for Shima" 2020-06-26 17:34:05 -07:00
qctecmdr
0185a28f00 Merge "dt-bindings: Add snapshot of smb1355 documentation" 2020-06-26 17:34:05 -07:00
Chris Lew
5b2a2b884c dt-bindings: mailbox: Add compatible for sdxlemur
Add compatible string for sdxlemur to the qcom,apcs-kpss-global driver.
This enables a mailbox interface for sending IPC interrupts.

Change-Id: Ied6bc10dfa35f31e64639fc34dc6d4fc14fd11fe
2020-06-26 16:03:30 -07:00
Kavya Nunna
407f557ef4 ARM: dts: msm: Include sdxlemur stub regulator
Include sdxlemur stub regulator file in target
specific file. Also rename "lemur-stub-regulator.dtsi"
to "sdxlemur-stub-regulator.dtsi".

Change-Id: Ie9428d7f5fe81c032c5dba28d3909b290e133aa0
2020-06-26 02:31:42 -07:00
Naveen Yadav
455b66c264 ARM: dts: msm: Add dummy clock nodes for clock controllers for SDXLEMUR
Dummy clock nodes are required for clocks client to request, so add
support for the same. Also add the dummy GDSCs required by clients.

Change-Id: I395914138a6ce3bd0b4d1467100d6bd9a53c6198
2020-06-26 13:58:12 +05:30
qctecmdr
fe2e418d24 Merge "ARM: dts: msm: Add Video FW image name" 2020-06-25 19:09:40 -07:00
qctecmdr
a28a5bd55b Merge "dt-bindings: msm: vidc: Add fw name dt property" 2020-06-25 19:09:40 -07:00
Guru Das Srinagesh
df0a3e3954 ARM: dts: msm: Enable symmetry in Lahaina led switch devices
On platforms where the led channels are connected pair-wise, enabling
symmetry causes the requested led current to be distributed equally
amongst them.

This is required because internally, the paired led channels are pulled
down by default, and turning only one of them on can cause some leakage
current to drain to the one that is off.

Change-Id: I08814be0b15bab9f9bb5aa640afd7635171dfc76
2020-06-25 15:37:01 -07:00
qctecmdr
401531e6ae Merge "bindings: smb1398: Add binding documents for SMB1398 charger" 2020-06-25 04:55:00 -07:00
qctecmdr
876b438ccf Merge "ARM: dts: msm: Adding shared-cb adsprpc-smd for Shima" 2020-06-25 04:54:59 -07:00
Taniya Das
d9de098b70 ARM: dts: msm: Update RPM-SMD clock node for HOLI
Update rpmcc clock node to support the rpm-smd clocks.

Change-Id: Ifdcad5b554a37dbb68c881e61f3c9b33b3f8a6d7
2020-06-25 16:40:14 +05:30
qctecmdr
9126bff286 Merge "ARM: dts: msm: Add imem node for sdxlemur" 2020-06-25 01:48:41 -07:00
Jishnu Prakash
0994ac19bb ARM: dts: msm: Add VADC and ADC_TM nodes for holi
Add VADC and ADC_TM nodes for thermistor channels for PM7250b, PM6150l
and PMK8350 on holi. Add corresponding thermal zones for thermistors.

Change-Id: I6db09f2b214d1d65a202f3134aae65610cd0d429
2020-06-25 11:32:19 +05:30
qctecmdr
9cb9ad2fe0 Merge "ARM: dts: qcom: Add thermal configuration for SHIMA" 2020-06-24 22:34:00 -07:00
qctecmdr
c09ed7a9c7 Merge "ARM: dts: msm: remove fastmap usage for uC/WLAN CBs on Lahaina" 2020-06-24 22:34:00 -07:00
qctecmdr
0548728ae5 Merge "ARM: dts: msm: add coresight device tree for holi" 2020-06-24 22:34:00 -07:00
qctecmdr
87d81c9868 Merge "ARM: dts: msm: Update the mem timer frequency" 2020-06-24 10:04:11 -07:00
qctecmdr
fc1a5ef298 Merge "bindings: pinctrl: Add device-tree bindings for SDXLEMUR pinctrl driver" 2020-06-24 10:04:11 -07:00
qctecmdr
88ed68fcf5 Merge "ARM: dts: msm: Add VADC and ADC_TM thermistor nodes for shima" 2020-06-24 02:45:24 -07:00
qctecmdr
a1c2eb9fb2 Merge "ARM: dts: msm: Add holi video dtsi in target dtsi" 2020-06-24 02:45:24 -07:00
Pavankumar Kondeti
977848406d ARM: dts: msm: Update capacity-dmips-mhz values for Shima
Update capacity-dmips-mhz value for prime CPU in Shima.

Change-Id: I61f5a5229d9f8564b6a47bba25177c743a954319
2020-06-24 13:07:26 +05:30