When scaling down to DDR mode we are passing 52Mhz to mmc_set_clock.
The SDHC requires internal clock frequency to be double the actual clock
that will be set for DDR mode. The controller uses the faster
clock(100/400MHz) for some part of SDHC internal h/w logic and send
the actual required clock (50/200MHz) to the card.
So in sdhci_msm_set_clock we multiply the clock by 2 for DDR modes.
Finally when we set host clk rate to 104Mhz then it scales to the nearest
equal or larger value which is 192Mhz for sdcc1_apps clk as per clk
drivers.
High frequency of 192Mhz for DDR52 mode leads to CRC errors for some
targets.
Hence Set the frequency to 50Mhz instead of 52Mhz.
Change-Id: I1d536db1dec4dfe16f41fd66362819c6db362901
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
Currently composite driver is calling get_status for the function
drivers which supports remote wakeup capability. Instead of this
have another judgement to check whether the device is advertising
remote wakeup capability.
Change-Id: I6e907b2a05ea64e04aa50ee90c4eb53b86b027d4
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
Add a new gen_headers file for auto targets to avoid
conflicts with mobile targets.
Change-Id: I95b59d8cb34b2d45c76eff42a5709fb905dff7ce
Signed-off-by: Venkata Rao Kakani <vkakani@codeaurora.org>
Update the android/abi_gki_aarch64_qcom with recent symbol additions.
Simple change and no need to update the .xml file, as no new symbol
addition.
Bug: 179747683
Signed-off-by: Neeraja P <neerp@codeaurora.org>
Signed-off-by: Kamal Agrawal <kamaagra@codeaurora.org>
Change-Id: I1d5252ed623f83611a5b064a8e0e33e4f0d188c5
The changes enables low latency for 120 priority FG binder
transactions in the rendering path.
Change-Id: I5736611c7f139362c54d0f0e73f07dfe078c8848
Signed-off-by: Kishore Sri venkata Ganesh Bolisetty <bsrivenk@codeaurora.org>
Currently driver uses random MAC address which gets changed
across composition switches or reboots. Allow user to specify
MAC address using configfs parameter to fix this.
Change-Id: I96710b3419ff7c016b931195a80ce77cd8c9038c
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Some clocks are critical only on specific boards, i.e. clocks used to
interface with external PMICs over I2C. Which clocks are critical depend
on which I2C bus is chosen to connect the PMICs. To support this, add
properties to set QCOM_CLK_IS_CRITICAL on a per-board basis.
The qcom,critical-clocks property can be used to set
QCOM_CLK_IS_CRITICAL on individual clocks.
The qcom,critical-devices property can be used to set
QCOM_CLK_IS_CRITICAL on all clocks used by specified devices.
Change-Id: I42d61ec13225026ba7d0b78079cf7a2ab67339f2
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Dump limited set of pcie PARF, DBI and PHY registers for
hang event.
Change-Id: I626bb25abac19a9194669532cc8bc77dbfad119d
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
Add QCOM_CLK_IS_CRITICAL, which can be used to enable a clock by default
in HW and to skip registering it with the framework.
Change-Id: I803a447fae742ca2e20973046090d2b8331ab598
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
enable qcom_scm and fastcvpd for vidc driver.
Change-Id: Idb17a079e1472e1d2a853d2ea68da6933768d7e1
Signed-off-by: Laisheng Hu <laisheng@codeaurora.org>
Consider a case where ep0 is not in setup stage and composition
switch happens. Currently DWC3_DEPCMD_ENDTRANSFER command is not
issued on ep0 which means that the transfers are not flushed out
and driver clears the run/stop bit hence stopping the controller.
Now as soon as driver sets the run/stop bit controller tries to
access the trb from the previous session which is already unmapped
resulting in SMMU fault.
Fix this by unconditionally issuing DWC3_DEPCMD_ENDTRANSFER
command on ep0. Although it is not specified in the data book
but if we know for sure that we are anyway going to stop the
controller then we can issue ENDTRANSFER command on ep0.
Change-Id: Ic6ee570acc8926897d3b6042181a501a47438d92
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
This can ease the complexity to port CNSS2 driver to non-MSM
platforms while still be able to maintain the compatibility.
Change-Id: I268cdd90c59085b34aa2fe3c3b845d60c4e2a417
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Since there may be link issues if QCA6490 device boots up with Gen3
link speed, always set initial target PCIe link speed to Gen2. Device
is able to change it (back) later at any time if needed.
Change-Id: I9d617d71926fe98e59e67aff772984878e0a2689
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Remove CONFIG_SLUB_DEBUG_ON from debug variant for performance
reasons. Also remove redundant HARDENED_USERCOPY from debug config
since this gets copied over from the standard config.
Change-Id: I7c6fc8620290cf126ced046f82811e9e39bc2a60
Signed-off-by: Dennis Cagle <dcagle@codeaurora.org>
Export clk_hw_register_composite() to support user built as module.
ERROR: modpost: "clk_hw_register_composite" [drivers/clk/imx/mxc-clk.ko]
undefined!
(cherry picked from commit d7d7518fdcc8f43da69fb40073273e77f24be24f)
[Jindong: Resolved minor conflict in drivers/clk/clk-composite.c ]
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
Change-Id: I54496d44d4bf6599af3a3ec9c40c02556d55cf17
There are usecases where clients want to change the maximum GEN
speed that PCIe can link up with. Provide clients the ability to
control the maximum PCIe GEN speed to for such usecases.
Change-Id: I834bee2063133546c9b0ebac2d5328ffbc5ceac6
Signed-off-by: Tony Truong <truong@codeaurora.org>
In HS Only mode of dwc3 controller version 1.9A, UTMI clock needs
to be selected before core soft reset as per the HPG sequence.
Or else the core soft reset fails, leading to enumeration
failure. Hence select UTMI clock before performing
SOFT_RESET operation.
Change-Id: I12d4a992872eecbfc38825282559cd4d592c3896
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
For non-MSM platforms, PCI wake GPIO may not be handled by PCI root
complex driver so add support to handle it in device driver.
Change-Id: Ief6bc6b25bdc5b93887af1cc626acc721f9fa85a
Signed-off-by: Yue Ma <yuem@codeaurora.org>
