Commit graph

631 commits

Author SHA1 Message Date
qctecmdr
047fc535bc Merge "ARM: dts: msm: Restrict default CMA region below 0xE0000000" 2020-02-07 18:53:33 -08:00
qctecmdr
19da0a4233 Merge "ARM: dts: msm: set MSR range in CSR for Lahaina" 2020-02-06 18:37:43 -08:00
qctecmdr
92428b423b Merge "dt-bindings: extcon-usb-gpio: Document optional vbus-out-gpio" 2020-02-06 18:37:43 -08:00
Liam Mark
69aff4ccaa ARM: dts: msm: Restrict default CMA region below 0xE0000000
Restrict default CMA region below 0xE0000000 so that allocations
from this region don't overlap with CLADE address range.

Change-Id: I462a70900b821ba1ff0fcb5ad020e79f37f6efb0
2020-02-06 17:10:20 -08:00
qctecmdr
6333ba36ef Merge "ARM: dts: msm: Hot fix for Lahaina" 2020-02-06 01:26:16 -08:00
qctecmdr
182f603513 Merge "ARM: dts: msm: enable PCIe0 and PCIe1 on lahaina" 2020-02-06 01:26:15 -08:00
qctecmdr
bd447a6628 Merge "ARM: dts: msm: Update fastrpc SIDs and masks" 2020-02-06 01:26:15 -08:00
Asutosh Das
bb3ce26b4a ARM: dts: msm: Hot fix for Lahaina
This change adds reset handle for ufsphy.
It also disables lpm.

Change-Id: Ica5dc3c9983646d44b8c534f267138c2b790e841
2020-02-05 09:25:05 -08:00
qctecmdr
1351fca9db Merge "ARM: dts: qcom: Update limit-rate and add limit-phy-submode on Lahaina" 2020-02-05 05:46:23 -08:00
qctecmdr
32f909194b Merge "ARM: dts: msm: add PMIC Glink and clients for Lahaina" 2020-02-05 05:46:23 -08:00
qctecmdr
7efeef6d98 Merge "ARM: dts: msm: Add PWM and RGB LED devices for PM8350C" 2020-02-05 01:00:30 -08:00
Tony Truong
e916f4a7b9 ARM: dts: msm: enable PCIe0 and PCIe1 on lahaina
Enable PCIe0 and PCIe1 on lahaina.

Change-Id: I9b57d69184e69494f8f6b18e8fd6a52114bc790b
2020-02-04 22:17:47 -08:00
qctecmdr
95b5fad106 Merge "ARM: dts: msm: Update changes for audio device tree on Lahaina" 2020-02-04 20:17:08 -08:00
qctecmdr
4c5a71049f Merge "ARM: dts: msm: Enable video driver" 2020-02-04 20:17:08 -08:00
qctecmdr
20f0f73270 Merge "ARM: dts: msm: Add secure display heap" 2020-02-04 20:17:08 -08:00
Subbaraman Narayanamurthy
3969e51429 ARM: dts: msm: add PMIC Glink and clients for Lahaina
Add PMIC Glink device and their client devices. PMIC Glink device
with name PMIC_RTR_ADSP_APPS supports the clients UCSI, battery
charger etc. PMIC Glink device with name PMIC_LOGS_ADSP_APPS
supports the client battery debug device.

Change-Id: Ia3bf0a0a0bb402e2c0a4def8ae343cbf762e0673
2020-02-04 19:13:50 -08:00
Edgar Flores
2697d27fa0 ARM: dts: msm: Update fastrpc SIDs and masks
Update fastrpc SIDs and masks context banks 1-9 for Lahaina.

Change-Id: I3e1c7d5e1e64eea8b6eb9b6e8cd487fe8aea2598
2020-02-04 16:18:45 -08:00
qctecmdr
2e8826e382 Merge "ARM: dts: qcom: switch to I2C control of PM8008 PMIC regulators for Lahaina" 2020-02-04 15:25:02 -08:00
David Collins
42d05762c7 ARM: dts: qcom: add VDD_MX and CX subnodes for MMCX dependencies on Lahaina
Add VDD_MX and VDD_CX rpmh-regulator subnodes which are used by
the VDD_MMCX regulator device.  Configure these sub nodes so that
a request for VDD_CX >= minimum operating level is present any
time that VDD_MMCX is enabled.

This ensures that multimedia hardware blocks are not accidentally
reset due to VDD_MMCX being enabled when VDD_CX is not enabled.

Implement the following <child> --> <parent> supply dependencies:

pm8350c_s8_level (MMCX)        --> pm8350_s5_mmcx_sup_level (MxA)
pm8350_s5_mmcx_sup_level (MxA) --> pm8350_s9_mmcx_sup_level (MxC)
pm8350_s9_mmcx_sup_level (MxC) --> pm8350c_s6_mmcx_sup_level (CX)

Note that the final MxC to CX supply dependency only propagates
the enable state of the regulator, not the voltage level.  This
ensures correctness while also minimizing power consumption.

Change-Id: Ib1c7d4fa685e88d62c7e31b1e6a1ae396aed4edb
2020-02-04 11:42:52 -08:00
Mihir Ganu
47a5954e2d ARM: dts: msm: Enable video driver
Enable vidc driver through device tree entry.

Change-Id: I58f51a23cd4fab6c0b29e2daf945dcf48613f058
2020-02-04 10:18:04 -08:00
Can Guo
ddb0ceb64b ARM: dts: qcom: Update limit-rate and add limit-phy-submode on Lahaina
Update limit-rate, 1 stands for Rate-A, 2 stands for Rate-B. In addition,
add limit-phy-submode to select UFS PHY submode used for PHY calibration.

Change-Id: Ifd0d55c0148256cd43d676b3b035c069ebb29fe2
2020-02-04 04:38:12 -08:00
qctecmdr
9ac22f5f04 Merge "ARM: dts: qcom: change all rpmh-regulator LDO default modes to HPM" 2020-02-04 03:48:05 -08:00
Tingwei Zhang
16684a9ffc ARM: dts: msm: set MSR range in CSR for Lahaina
Set the MSR register range in SWAO CSR for Lahaina.

Change-Id: I430c9d1ba20abc32c9e3879b42ffa2e7cbd351c8
2020-02-03 23:26:53 -08:00
qctecmdr
329489d312 Merge "ARM: dts: msm: add initial PHY sequence for PCIe0 and PCIe1 on lahaina" 2020-02-03 14:44:47 -08:00
qctecmdr
e4e59c5761 Merge "dt-bindings: Add snapshot of QPNP AMOLED regulator bindings" 2020-02-03 14:44:47 -08:00
qctecmdr
90027b86f5 Merge "ARM: dts: msm: Fix secondary USB port related aggre_noc clock" 2020-02-03 14:44:47 -08:00
Jack Pham
dd3a308306 dt-bindings: extcon-usb-gpio: Document optional vbus-out-gpio
Document bindings for optional vbus-out-gpio which is used to
turn on VBUS when the ID pin is detected low and the port
enters USB host mode.

Change-Id: I1c91da47c006f79e85bcf8fef5791cfde6de70fb
2020-02-03 14:42:11 -08:00
Sudheer Papothi
70654b9613 ARM: dts: msm: Update changes for audio device tree on Lahaina
Update changes for audio device tree on Lahaina.

Change-Id: If52eb0d3451626c62f6afb565c6112ebf2475692
2020-02-04 04:02:06 +05:30
Mayank Rana
b68e50a3b0 ARM: dts: msm: Fix secondary USB port related aggre_noc clock
USB device failed to enumerate with USB host as USB bus aggre_noc
was not enabled related to secondary USB controller. Fix this issue
by using correct aggre_noc clock handler.

Change-Id: I8a8cc75911a37df705f6d1389b3771a6b6982f41
2020-02-03 13:12:31 -08:00
qctecmdr
d13380a8bf Merge "ARM: dts: msm: Fix ufs OCS error" 2020-02-03 10:02:57 -08:00
Tony Truong
434074aeab ARM: dts: msm: add initial PHY sequence for PCIe0 and PCIe1 on lahaina
Add initial PHY sequence for PCIe0 and PCIe1 on lahaina.

Change-Id: Ic604830066e353202fb9234951ae2765f4e7b00a
2020-02-03 09:18:52 -08:00
Tony Truong
7f4bcfef39 ARM: dts: msm: add PCIe pipe clk mux and ext src to PCIe clock for lahaina
PCIe needs to switch between XO and pcie_*_pipe_clk based on
LPM state. Add the clocks to support this on lahaina.

Change-Id: I44efe4752d5a9d93a7fff5809b272fa4b6146f14
2020-02-03 09:18:48 -08:00
Tony Truong
60f5940600 ARM: dts: msm: add aggre_noc_pcie_*_axi_clk for PCIe on lahaina
Add aggre_noc_pcie_0_axi_clk and aggre_noc_pcie_1_axi_clk for
the corresponding PCIe devicetree node on lahaina.

Change-Id: Ic5940f38b83b54aeb77d310b144a75e15c72b74f
2020-02-03 09:18:44 -08:00
qctecmdr
d03820b8f6 Merge "ARM: dts: msm: Disable watchdog for Lahaina-RUMI" 2020-02-02 17:26:40 -08:00
qctecmdr
f44b1b4db1 Merge "ARM: dts: msm: Do not create logical mappings for the secure CDSP heap" 2020-02-01 21:26:28 -08:00
David Collins
0d9d1080f2 ARM: dts: qcom: change all rpmh-regulator LDO default modes to HPM
Change the initial mode of all rpmh-regulator LDO devices from
low power mode (LPM) to high/normal power mode (HPM).  This
avoids problems during boot up if a consumer requests a voltage
before requesting a load current as this will result in the
LDO regulator being switched to LPM.  A subsequent load current
request will switch it to HPM.  However, if the LDO was enabled
and sourcing more current than the LPM limit, then this brief
period can cause the voltage to drop out and lead to hardware
faults.

Change-Id: Ibecd9c439a6b382642a6131eecb92c2a50f64a05
2020-01-31 16:57:32 -08:00
qctecmdr
66bb91ca95 Merge "dt-bindings: input: qcom-hv-haptics: Add initial binding document" 2020-01-31 16:56:06 -08:00
qctecmdr
fe5692f1c8 Merge "ARM: dts: msm: Specify address/size cells for &soc on lahaina-rumi" 2020-01-31 16:56:05 -08:00
qctecmdr
46239aacf8 Merge "ARM: dts: msm: Add interconnects to USB on Lahaina" 2020-01-31 16:56:05 -08:00
Isaac J. Manjarres
38156f438c ARM: dts: msm: Do not create logical mappings for the secure CDSP heap
Creating logical mappings for the secure CDSP heap memory may
cause problems with respect to speculative access, so ensure
that no logical kernel mappings are created for that region.

Change-Id: I56c23e82c1a4ba52322aa0f5a2045e482a8586ff
2020-01-31 13:53:07 -08:00
Raghavendra Rao Ananta
a542936ef7 ARM: dts: msm: Disable watchdog for Lahaina-RUMI
As the emulation platform is very slow, we may encounter watchdog
barks/bites very often. Hence, explicitly disable the device-tree
node for the watchdog driver for this platform.

Change-Id: I11e48439370efdd27c2c6cee6798fe0d22e2bd7d
2020-01-31 10:39:33 -08:00
Raghavendra Rao Ananta
11877cd88d ARM: dts: msm: Update the arch_timer frequency
Update the arch_timer frequency to 19.2 MHz, now that the device
boots up on a real hardware (instead of an emulation platform).
Leave the 96KHz still intact for emulation platforms.

Change-Id: I3745395b88d8aa9d1b0047b4eca7c85db4ec7a13
2020-01-31 10:39:33 -08:00
qctecmdr
40cf535cc0 Merge "ARM: dts: msm: Fix USB PHY resets" 2020-01-31 10:27:17 -08:00
qctecmdr
cc7e741fc8 Merge "ARM: dts: msm: Add alias for HSUART node" 2020-01-31 10:27:17 -08:00
qctecmdr
29348badb7 Merge "bindings: pinctrl: Add device-tree bindings for Lahaina pinctrl driver" 2020-01-31 04:38:34 -08:00
qctecmdr
0141f892dd Merge "ARM: dts: msm: vidc: Add register value mask" 2020-01-30 23:05:03 -08:00
qctecmdr
f5febf26bd Merge "ARM: dts: msm: Include ipcc_test dtsi file in lahaina.dtsi file" 2020-01-30 23:05:03 -08:00
Jack Pham
cecd0dc415 ARM: dts: msm: Specify address/size cells for &soc on lahaina-rumi
When lahaina-rumi is compiled as a separate overlay, it does
not explicitly include the definition of the &soc node. Without
the #address-cells and #size-cells specifiers, the compiler uses
default values of 2 and 1, respectively, which results in the
following warnings when compiling lahaina-rumi-overlay.dtb:

  Warning (reg_format): "reg" property in
/fragment@15/__overlay__/usb_emu_phy@a720000 has invalid length (8
bytes) (#address-cells == 2, #size-cells == 1) Warning
(avoid_default_addr_size): Relying on default #address-cells value for
/fragment@15/__overlay__/usb_emu_phy@a720000
  Warning (avoid_default_addr_size): Relying on default #size-cells
value for /fragment@15/__overlay__/usb_emu_phy@a720000

As the &soc node is referenced here only for the purpose of adding
a new child node, usb_emu_phy, address the warnings by explicitly
defining the {address,size}-cells values.

Change-Id: I8b5ebcd53c060eeea3c55bf9fb8e55093e7862f2
2020-01-30 22:45:35 -08:00
Fenglin Wu
11444a63a7 dt-bindings: input: qcom-hv-haptics: Add initial binding document
Qualcomm Technologies, Inc. (QTI) High Voltage (HV) PMIC haptics
modules can support up to 10 V voltage to drive either ERM or LRA.
It has an integrated module to support auto resonance detection
and correction for LRA actuator. It can play different vibration
effects with different pattern sources. It also has an integrated
brake module which can work in different modes to use BEMF for
quick vibration stop.

Change-Id: Id8b9fa1e4eefc7dda325e25728e59af9c1de9049
2020-01-30 18:00:40 -08:00
Akshay Chandrashekhar Kalghatgi
2036e44c56 ARM: dts: msm: Add secure display heap
Add a secure display heap of size 164 MB for carveout memory
required to support 3 concurrent secure Video sessions.

Change-Id: I5d88df171370e7f3cc9ad723db1d2736e1bf614f
2020-01-30 16:50:20 -08:00