Porgramming guide for tcu clock testbus controller says:
1) Write to the ARM_SMMU_TESTBUS_SEL_HLOS1_NS.
2) Read from the ARM_SMMU_TCU_TESTBUS_HLOS1_NS
to know the internal smmu clock status. Program them accordingly.
Change-Id: I6140d877c2d8366030699fb04099078ebb3b6e2c
Fixes: 47b2cb7ab2 ("iommu: arm-smmu: update access to SMMU TCU testbus registers with scm call")
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
SPI Transfer mode selection is based on length but in SPI responder case
we get some latency for FIFO mode transfer that will cause some delay
in SPI responder transfer and we get "TX_FIFO_RD_ERR" interrupt. Moving
SPI responder to DMA mode for all transfer will not have this latency
issue and SPI requester/responder will be in sync and we won't get any
error related to SPI requester/responder sync.
Change-Id: I6b9676aad2a4875a9ff6c4d998a45d2cd8a14cfa
Signed-off-by: Ashish Kori <akori@codeaurora.org>
Ensure usbch is ready before usb bypass start to avoid usbch is NULL
in usb_read_work_fn().
Change-Id: I0b932f1713a2d49424860728e79e3684122b4e40
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
Enable linux bridge on QGKI builds to support multi-AP bridge mode.
Change-Id: I1c8278b3ca29d973ea5350028c8f065370e91271
Signed-off-by: wadesong <wadesong@codeaurora.org>
Add mproc related defconfig for sa8155 which inlcudes
qrtr,hwspinlock,mailbox,glink,smem,smp2p,ipc irq bridge
and ipc logging related configurations.
Change-Id: I64e8feea35a0acabf48e538dfe9e7bdd3b547b11
Signed-off-by: Arun Prakash <app@codeaurora.org>
Currently the driver explicitly clears the HWO bit of the TRB
prepared for short packet or ZLP for EPs in both the directions,
and returns with non-zero code which breaks cleanup of completed
requests. The driver does this because it is written with the
understanding that the HW does not clear HWO for such packets.
But the databook section 4.2.3.2 says that the HW does not clear
HWO for such packets on the OUT EP only.
Now consider a device-to-host(USB IN) usecase like SW NCM, where
the u_ether driver looks for interrupt on every 5th request(say).
In between these 5 requests, if there is any packet of multiple
of MPS, then ZLP TRB will also be prepared. When the event is
received for the 5th request, we will only handle upto the ZLP
TRB because of the faulty logic described above. And only on the
event for the 10th request, we handle the 5th request (because of
IOC set on the 5th request). So, clearly the TRB cleanup logic is
lagging behind the HW actually completing the requests. When this
mismatch happens multiple times, there eventually comes a time
when the SW does not have any free requests anymore and hence
stall will be seen.
Fix this by returning with non-zero code only if the IOC bit is
set for the short packet or ZLP TRB, so that the cleanup routine
continues upto the TRB for which the event was raised.
Change-Id: I984e6de383993fc3c2da6b74147d6f50e081de34
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Add property to configure the default trigger for the LED.
This will allow clients to use trigger APIs to configure
the brightness of the LED if needed.
Change-Id: I1db0a5f2d697c6ac6f6ae1296e43ae55509f2298
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
slatecom driver provides a set of apis to perform
register, fifo, ahb read and write operations with
slate coprocessor over spi interface.
slatecom driver is ported from bgcom driver.
Change-Id: Ibaacf4748d893511196e4a66ed17ff26a854809b
Signed-off-by: Ajit Kumar <kajit@codeaurora.org>
Add CONFIG options to get the number of AMUs and PMUs supported on
a given target to define the size of structures accordingly in driver.
Change-Id: I6ed58465f789156887a28bd49da7220396854e50
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
