Commit graph

3,293 commits

Author SHA1 Message Date
qctecmdr
b7838e4ef4 Merge "ARM: dts: msm: Update BCL, Alarm and CPU thermal mitigation for SHIMA" 2020-11-26 05:30:40 -08:00
qctecmdr
663f600397 Merge "dt-bindings: input: qpnp-power-on: Update "reg" property description" 2020-11-26 00:33:35 -08:00
qctecmdr
d794724a84 Merge "ARM: dts: msm: add no-memory-wc to sram node for holi" 2020-11-26 00:33:35 -08:00
qctecmdr
421c0aa6d2 Merge "ARM: dts: msm: remove SMB1398 clock frequency setting on holi" 2020-11-26 00:33:35 -08:00
qctecmdr
38eb94ccfb Merge "ARM: dts: msm: Update interconnect nodes for YUPIK" 2020-11-26 00:33:35 -08:00
Santosh Mardi
a2607bacd2 ARM: dts: msm: add no-memory-wc to sram node for holi
This flag indicates to the driver that SRAM memory region
has not to be remapped as write combining.

Change-Id: I05529a30066d373ce1fad9a88a6f18e9e4467b64
2020-11-25 05:54:26 -08:00
Kiran Gunda
ea9228516a dt-bindings: input: qpnp-power-on: Update "reg" property description
Update the description of "reg" property to add the PON_PBS base
address along with PON_HLOS base address. Also add "reg-names"
property.

Change-Id: I257950babd4b68f3ab933679bd94936813531e25
2020-11-25 04:35:08 -08:00
Odelu Kukatla
3b55265d6c ARM: dts: msm: Update interconnect nodes for YUPIK
Add bcm voter devices that live under RSC devices
to allow interconnect providers to target their
votes for meeting bandwidth constraints. Also update
the interconnect nodes so that real provider drivers
get probed.

Change-Id: I2359c9b2b789891045d2d70f83d5b19ebc529646
2020-11-25 03:16:54 -08:00
Odelu Kukatla
4b0a5adb19 dt-bindings: interconnect: update interconnect bindings
Update interconnect device bindings. These devices can be
used to describe any RPMH and NoC based interconnect devices.

Change-Id: I4bca29bda915717690efd24bf80ce1e3bd3b4154
2020-11-25 03:15:34 -08:00
Gopala Krishna Nuthaki
ddaae4656a ARM: dts: msm: Update BCL, Alarm and CPU thermal mitigation for SHIMA
Update the BCL rule in SHIMA to include CDSP mitigation for
all three violations.

Update PM8350 alarm rule in SHIMA to have cpufreq as mitigation
devcie instead of cpu-isolate cooling device for silver and gold
cores.

Update silver core mitigation to ensure minimum operating
performance.

Change-Id: I5ba29ee1e606cf9104e4ab4745606c473b9ea497
2020-11-25 00:37:29 -08:00
Gopala Krishna Nuthaki
c44ace7d56 ARM: dts: msm: Update thermal mitigation config for SHIMA
Update quiet-therm sensor skin thermal zone mitigation config
for SHIMA based on latest recommendation.

Add modem lte sub6 skin sensor based thermal zone mitigation
config for SHIMA on latest recomondation.

Change-Id: I1305de5650dae6d234fc4338b0dee9665a2c844d
2020-11-25 00:16:47 -08:00
qctecmdr
babb6bac5c Merge "ARM: dts: msm: refine QDSS config for sdxlemur" 2020-11-24 22:12:51 -08:00
qctecmdr
0193a0e00c Merge "ARM: dts: msm: modify dcc_ram_offset for sdxlemur" 2020-11-24 22:12:51 -08:00
Jishnu Prakash
1fe6660ca9 ARM: dts: msm: remove SMB1398 clock frequency setting on holi
Remove SMB1398 setting to change qupv3_se10_i2c clock frequency
to 100kHz as it is not needed for SMB1398 v2 and v3.

Change-Id: I65534d7fca92b9f494807b5d08944c766903d31c
2020-11-25 11:39:49 +05:30
qctecmdr
0f8c066abf Merge "ARM: dts: msm: Update GPUCC clock node and GDSC for YUPIK" 2020-11-24 12:44:42 -08:00
qctecmdr
00699aaa53 Merge "ARM: dts: msm: Add dma-coherent for tmc-etr on Lahaina" 2020-11-24 12:44:42 -08:00
qctecmdr
4f22025022 Merge "ARM: dts: msm: Add UFS support for SA8155" 2020-11-24 12:44:42 -08:00
qctecmdr
6da3342136 Merge "ARM: dts: msm: DDR cooling device no mitigation for lahaina" 2020-11-24 12:44:42 -08:00
qctecmdr
bd9514b700 Merge "ARM: dts: msm: Add Wakeup interrupt controller for scuba-iot" 2020-11-24 09:02:36 -08:00
qctecmdr
0203f7374b Merge "ARM: dts: msm: Reduce secure heap to 30MB" 2020-11-24 09:02:36 -08:00
qctecmdr
687213cf60 Merge "ARM: dts: msm: Add ARM PMU node for Yupik" 2020-11-24 09:02:35 -08:00
qctecmdr
82be7afb66 Merge "ARM: dts: msm: Enable NAND and SD card for sdxlemur target" 2020-11-24 09:02:35 -08:00
qctecmdr
a4be9294fd Merge "ARM: dts: msm: Support CNSS WLAN device for sdxlemur" 2020-11-24 09:02:35 -08:00
qctecmdr
194ade0109 Merge "ARM: dts: msm: Enable bluetooth for sdxlemur" 2020-11-24 09:02:35 -08:00
qctecmdr
49ba4d66e2 Merge "ARM: dts: msm: Change the node location for optimization for Shima" 2020-11-24 05:19:03 -08:00
qctecmdr
cf8f31bf2a Merge "ARM: dts: msm: Add QUPv3 SE and GPI DT nodes for yupik" 2020-11-24 05:19:03 -08:00
qctecmdr
4fdbd047ca Merge "ARM: dts: msm: Add Bus voting support" 2020-11-24 05:19:03 -08:00
qctecmdr
cf08033767 Merge "ARM: dts: msm: Disable scaling for SD and eMMC on sdxlemur" 2020-11-24 05:19:02 -08:00
Yuanfang Zhang
46d06ca5d9 ARM: dts: msm: modify dcc_ram_offset for sdxlemur
Modify dcc_ram_offset to 0x12000 on sdxlemur.

Change-Id: Iadb7d0ce55976cb9a29fdc6d57b4ea46783bc6b1
2020-11-24 17:57:07 +08:00
Yuanfang Zhang
61540c97eb ARM: dts: msm: refine QDSS config for sdxlemur
Add reset and flush trigger number for etr and etf.

Change-Id: Iec420ee00ac45ca37e525f3736e0204d6c36e71b
2020-11-24 17:54:50 +08:00
Veera Vegivada
24f8b6eb0b ARM: dts: msm: Add UFS support for SA8155
Add UFS host controller and UFS PHY (attached to embedded UFS card)
for SM8150 platform and SA8155.

Change-Id: I2f58f3bd2457fed0baaffa5233bbd2c92ec22c12
2020-11-24 14:01:41 +05:30
Veera Vegivada
6236ec35c7 ARM: dts: msm: add interconnect devices for sm8150
Add stub interconnect devices for aggre1_noc, aggre2_noc,
camnoc_virt, compute_noc, config_noc, dc_noc, gem_noc,
ipa_virt, mc_virt, mmss_noc, system_noc, gem_noc_display,
mc_virt_display, mmss_noc_display. This will allow consumers
to get their path and set bandwidth constraints on them.
And add bcm voter devices that live under RSC devices
to allow interconnect providers to target their votes
for meeting bandwidth constraints.

Change-Id: I6c46d36928ecfbeaa5b568a61d3dfee9e9e0349d
2020-11-24 14:01:33 +05:30
Veera Vegivada
e8ca9d4eee ARM: dts: msm: Add clock controller and gdsc nodes for sm8150
Add support for all the clock controllers and also add
gdsc regulators.

Change-Id: Ic313db887845e43c1d69b82f6bd8af4154145832
2020-11-24 14:00:28 +05:30
Mao Jinlong
ae8150eac6 ARM: dts: msm: Add dma-coherent for tmc-etr on Lahaina
Add dma-coherent for tmc-etr to avoid cache flush issue between etr and
usb.

Change-Id: Iba762e88442294c93c22675f2b4d2c2937c1e9dd
2020-11-24 16:27:39 +08:00
qctecmdr
bd7b55b1f4 Merge "ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on shima" 2020-11-23 23:23:26 -08:00
qctecmdr
afd0f14ce4 Merge "ARM: dts: msm: keep PCIe in EQ Master Phase for at least 1ms on sdxlemur" 2020-11-23 23:23:26 -08:00
Sarthak Garg
aaf5337d63 ARM: dts: msm: Enable NAND and SD card for sdxlemur target
Enable NAND and SD card for all the boards available on sdxlemur target.

Change-Id: I17b3321bde161fbfbec8950d9893854912297ba9
2020-11-24 08:49:46 +05:30
qctecmdr
ca4817e692 Merge "ARM: dts: msm: Add dummy clock nodes for MONACO" 2020-11-23 19:13:31 -08:00
Zijun Hu
0e4ed0f335 ARM: dts: msm: Enable bluetooth for sdxlemur
Enable bluetooth for sdxlemur.

CRs-Fixed: 2824381
Change-Id: I37762923eb49bfb3b3bbb19a5f088540f473f4e4
2020-11-23 18:43:01 -08:00
Zijun Hu
5e9e8bc326 ARM: dts: msm: Add label for bluetooth bootstrap pin EDL_MODE on sdxlemur
GPIO17 also drives bluetooth bootstrap pin EDL_MODE for sdxlemur, so
add a label for bluetooth.

CRs-Fixed: 2824381
Change-Id: I3779e8fa26e9a41b6a0a378b4ed97b7b985bd2c1
2020-11-23 18:42:41 -08:00
Ram Chandrasekar
343beb8375 ARM: dts: msm: DDR cooling device no mitigation for lahaina
DDR cooling device right now votes for the lowest bandwidth when there
is no request from cooling device. Instead of voting to lowest level,
vote for zero bandwidth, so that it doesn't prevent sleep.

Change-Id: Ibf7895568f7c102bd4dc7267327b7decf45362e8
2020-11-23 16:06:53 -08:00
Wu Gao
68d9dff9f9 ARM: dts: msm: Support CNSS WLAN device for sdxlemur
Support CNSS WLAN device for sdxlemur.

Change-Id: I152ecbd2064b63f15ea38cc300531371d4c0d925
2020-11-23 21:36:34 +08:00
Saurabh Sahu
17cf51a99a ARM: dts: msm: Add dummy clock nodes for MONACO
Dummy clock nodes are required for clocks client to
request, so add support for the same. Also add the
dummy GDSCs required by clients for monaco.

Change-Id: I16e204fb2c04cbe750db25af4364a8af0b252404
2020-11-23 17:39:19 +05:30
qctecmdr
ccad25bb08 Merge "ARM: dts: msm: Add missing memory map region for sdxlemur" 2020-11-23 03:49:18 -08:00
qctecmdr
8aa7ad36ec Merge "ARM: dts: msm: Enable eMMC for sdxlemur target" 2020-11-23 03:49:18 -08:00
qctecmdr
2a1406de4e Merge "ARM: dts: msm: add spmi_debug_bus for sdxlemur" 2020-11-22 23:40:44 -08:00
qctecmdr
5750137b30 Merge "ARM: dts: msm: Disable PMX65 VBUS_DET on sdxlemur MTP-MBB and RCM-RC boards" 2020-11-22 23:40:44 -08:00
qctecmdr
3c2bdfedfc Merge "ARM: dts: msm: specify thermal mitigation levels for sdxlemur platforms" 2020-11-22 23:40:43 -08:00
qctecmdr
035ee046ce Merge "ARM: dts: msm: add gfx smmu node on yupik" 2020-11-22 23:40:43 -08:00
Sarthak Garg
696feed44e ARM: dts: msm: Disable scaling for SD and eMMC on sdxlemur
Disable scaling for SD and eMMC as for SD card the clocks were not
getting scaled properly.

Change-Id: Ic90f783ad141a9cb8e8bde10aacfd365aac3b3dc
2020-11-22 10:59:45 +05:30