Commit graph

878,451 commits

Author SHA1 Message Date
qctecmdr
ec907937b7 Merge "msm: kgsl: Enable the CX GSDC before accessing IOMMU registers" 2020-03-04 12:05:54 -08:00
qctecmdr
dc31b0d700 Merge "msm: pcie: Revert "scale CX and rate change after DRV resume"" 2020-03-04 12:05:54 -08:00
qctecmdr
4a24eecc1f Merge "defconfig: Enable CPU isolation cooling device for lahaina" 2020-03-04 12:05:54 -08:00
qctecmdr
f265cc530d Merge "msm: kgsl: Move GMU to a component device" 2020-03-04 09:11:42 -08:00
qctecmdr
c744f806b4 Merge "iommu/arm-smmu: Cleanup qsmmuv500_iova_to_phys_hard()" 2020-03-04 03:33:48 -08:00
qctecmdr
15db89de68 Merge "NFC: Add driver to configure NFC-I3C controller GPIOs" 2020-03-04 03:33:47 -08:00
qctecmdr
8a492f7f64 Merge "clk: qcom: update the DisplayPort clocks" 2020-03-04 00:26:50 -08:00
qctecmdr
3f59866d28 Merge "serial: msm_geni_serial: Set clock freq correctly for RUMI" 2020-03-04 00:26:50 -08:00
Jordan Crouse
1c6fcc54ec msm: kgsl: Enable the CX GSDC before accessing IOMMU registers
If needed, the IOMMU device can define a CX GDSC to enable before
turning on clocks to directly write IOMMU registers.

Change-Id: Ic0dedbadc8479cc36d5603d6d8a2c93133fda668
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-03-03 15:49:10 -07:00
Jordan Crouse
00a1ef124f msm: kgsl: Move the IOMMU clocks to the KGSL device
Move ownership of the IOMMU clocks to the KGSL device and get them from
there during IOMMU probe.  This ensures that the clocks are owned by a
proper platform device that can sync_state() after we are done probing.

Change-Id: Ic0dedbad97783984f7d8d1c3c2252a1a8a812d77
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-03-03 15:49:10 -07:00
Jordan Crouse
0c46c9a35b msm: kgsl: Move GMU to a component device
Traditionally the GMU/RGMU device has been a child of the adreno device
and probed manually. That has worked despite the fact that the GMU/RGMU
device has resources of its own and it really should be a top level
platform device.

Finally do the right thing, make GMU a top level platform device and
driver and bind it to Adreno as a component. This will make sure we
get the advantages of all of the platform level initialization without
having to code in half a dozen hacks to make everything work and then
break again next kernel version.

Change-Id: Ic0dedbadf6776e1a4f5e0eb1e093241e5103b3ff
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-03-03 15:49:09 -07:00
Jordan Crouse
c7ae23947d msm: kgsl: Minor cleanups for kgsl bus probe
The KGSL bus probe was not quite resilient for a deferred probe. Move
a memory allocation to devm and make sure that the interconnect handle
is properly put away on failure.

Change-Id: Ic0dedbad261c483a157161a43da0b54459ed46ff
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-03-03 15:49:09 -07:00
Tony Truong
d161462d9d msm: pcie: Revert "scale CX and rate change after DRV resume"
This reverts commit 603d76db80.

This change is already present in the snapshot. This revert
will remove duplicate code.

Change-Id: Id4588031a93c041a9480ac8ef33b6d177a4a2477
Signed-off-by: Tony Truong <truong@codeaurora.org>
2020-03-03 13:02:18 -08:00
Ram Chandrasekar
5f725f308b defconfig: Enable CPU isolation cooling device for lahaina
Enable CPU isolation cooling device driver. This driver will enable the
thermal framework to isolate the CPU cores on thermal conditions.

Change-Id: Ic1f04b7d341c6165d5e971f7dc03ad27bc721897
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2020-03-03 11:34:38 -08:00
Karthik Poosa
92d40d99da NFC: Add driver to configure NFC-I3C controller GPIOs
Add driver to toggle NFC GPIOs for I3C enumeration to
pass for NFC controller.

Change-Id: I3eef5b8a327c2c70355c03574b06bf67e26b4419
Signed-off-by: Karthik Poosa <kpoosa2@codeaurora.org>
2020-03-03 11:08:41 -08:00
qctecmdr
535241a5fb Merge "iommu/arm-smmu: Remove DOMAIN_ATTR_DEBUG" 2020-03-03 07:08:23 -08:00
qctecmdr
0f7dd8d723 Merge "msm: cvp: avoid OOB write while accessing memory" 2020-03-03 03:08:34 -08:00
Govindaraj Rajagopal
4267dcfae7 msm: cvp: avoid OOB write while accessing memory
Exclude 4 bytes which holds the size of the buffer while calculating
the actual buffer size to avoid OOB write.

Change-Id: I79704181e0bafc905064621d7cd6e682cca15982
Signed-off-by: suchawla <suchawla@codeaurora.org>
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-03-03 11:49:57 +05:30
qctecmdr
1b081c88d1 Merge "drm: Add DisplayPort colorspace property creation function" 2020-03-02 21:33:44 -08:00
qctecmdr
b090557030 Merge "iommu/arm-smmu: Rationalize TLB sync timeout handling" 2020-03-02 21:33:43 -08:00
qctecmdr
f3ed56f0e1 Merge "msm: pcie: add option to disable L1ss TO for DRV suspend" 2020-03-02 18:28:28 -08:00
qctecmdr
2194df887b Merge "msm: kgsl: Set default bus control to true" 2020-03-02 18:28:27 -08:00
qctecmdr
59c71da3d6 Merge "msm: kgsl: Make a device specific scales_bandwidth function" 2020-03-02 18:28:27 -08:00
Tatenda Chipeperekwa
897ebf670e clk: qcom: update the DisplayPort clocks
Update the frequencies of the clocks from Hz to KHz so that they
match the frequencies requested by the DisplayPort driver. This
ensures that the clock framework correctly scales parent clock
values for all DisplayPort clock requests.

Change-Id: I46be984340902f1facba59ad966e0f2ad1b1b006
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2020-03-02 17:04:59 -08:00
qctecmdr
f5b276ebbd Merge "interconnect: qcom: Remove duplicate compatible string" 2020-03-02 15:30:40 -08:00
Isaac J. Manjarres
a1536228ea iommu/arm-smmu: Cleanup qsmmuv500_iova_to_phys_hard()
qsmmuv500_iova_to_phys_hard() takes in the IOMMU domain as an
input parameter, but only uses it to derive the SMMU domain.
In preparation for moving this function out to a file where
to_smmu_domain() will not be available, require that the input
argument be an SMMU domain, instead of the IOMMU domain. This
change has no functional impact.

Change-Id: I2ac7efbae70df2378dc382d697dcfe7a676b85f2
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-02 12:14:33 -08:00
Isaac J. Manjarres
24edad3d95 iommu/arm-smmu: Remove DOMAIN_ATTR_DEBUG
DOMAIN_ATTR_DEBUG is queried by the qsmmuv500_iova_to_phys()
function, which will move outside of arm-smmu.c, requiring
arm_smmu_domain_get_attr() to be exposed, which doesn't make
sense for only one attribute.

Thus, remove this domain attribute and inform the SMMU driver
that it is operating on a debug domain by introducing a new
marker in the msm_iommu_domain for debug domains. This patch
has no functional impact.

Change-Id: I86dfbadab0a74f9018acc602eea28b2a3a2c38b5
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-02 12:14:32 -08:00
Isaac J. Manjarres
b5f2204f08 iommu/arm-smmu: Cleanup arm_smmu_init()
arm_smmu_init() has retained some workarounds for
back when it could be invoked multiple times as either
part of the initcall sequences, or through the IOMMU
OF table. This was necessary before the driver
core handled dependencies between an IOMMU master
and an IOMMU device. Since this is no longer the case,
we can remove this logic. Also, while we're here,
unregister the TBU driver if the SMMU driver cannot
be registered.

Change-Id: I5c2ed4a046c63babb3bd60390c468a4e5e27de6e
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-02 12:14:31 -08:00
Isaac J. Manjarres
90c4319e85 iommu/arm-smmu: Rationalize TLB sync timeout handling
The current TLB sync timeout handling doesn't make sense
in the context of non QSMMU-V500 SMMU V2 implementations, so
introduce the notion of architecture specific handling
for TLB sync timeouts.

Change-Id: Ibceb5422d6488f9e67cc4c4ed968348ad92aa834
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-02 12:14:26 -08:00
qctecmdr
1723ebdd64 Merge "msm: cvp: Add AXI reset pulse" 2020-03-02 11:58:08 -08:00
qctecmdr
e834b0464c Merge "usb: dwc3: Do not initiate remote wakeup from core layer" 2020-03-02 11:58:08 -08:00
qctecmdr
1dc2d12bba Merge "msm: kgsl: Remove the extra recovery hop" 2020-03-02 11:58:08 -08:00
qctecmdr
692509a8fa Merge "Merge fbe changes from upstream 5.4" 2020-03-02 11:58:08 -08:00
qctecmdr
0963e5d909 Merge "phy: ufs: Refactor phy_power_on and phy_calibrate callbacks" 2020-03-02 09:05:58 -08:00
qctecmdr
8b6560577f Merge "dt-bindings: clock: Add support for clock ids for SHIMA" 2020-03-02 09:05:58 -08:00
Jordan Crouse
88dcd53516 msm: kgsl: Make a device specific scales_bandwidth function
To make it easier for the upcoming change to move GMU to a component
device make a real function to test if the target is capable of
scaling the bus bandwidth on the GMU.

Change-Id: Ic0dedbad255622428de2ac01a5833a9e28c9c3ac
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-03-02 09:33:10 -07:00
qctecmdr
9ee272676c Merge "arm64: Honor limits set by boot parameter" 2020-03-02 04:36:30 -08:00
qctecmdr
1ab609531c Merge "arm64: mm: improve the mem-offline device node availability check" 2020-03-02 04:36:30 -08:00
qctecmdr
592ae25d40 Merge "defconfig: arm64: Enable data defconfigs" 2020-03-02 04:36:29 -08:00
qctecmdr
bdbcfb1ea2 Merge "msm: kgsl: Add A660 hardware clock gating register values" 2020-03-02 00:26:49 -08:00
qctecmdr
ca6ad9e77f Merge "iommu/arm-smmu: Cleanup context fault logging logic" 2020-03-02 00:26:48 -08:00
qctecmdr
fc4dced779 Merge "ion: don't wakeup refill threads for order-0 requests" 2020-03-02 00:26:48 -08:00
Can Guo
5409868760 phy: ufs: Refactor phy_power_on and phy_calibrate callbacks
Move UFS PHY calibration, starting serdes and PCS ready status polling
from phy_power_on callback to phy_calibrate callback.

Change-Id: I772978735f00ac31539eb3bec471d4d7e5f16d73
Signed-off-by: Can Guo <cang@codeaurora.org>
2020-03-01 21:04:01 -08:00
qctecmdr
201f211f2d Merge "sched: walt: Improve the scheduler" 2020-03-01 20:58:29 -08:00
Taniya Das
087303dadb dt-bindings: clock: Add support for clock ids for SHIMA
Add clock IDs for CAMCC/DISPCC/GCC/GPUCC/VIDEOCC for clients to be able to
request for clocks from these clock controllers.

Change-Id: Ic809b350cfb15d7dce4667907fe6176a7293bdcd
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2020-03-01 19:58:56 -08:00
qctecmdr
93655ae632 Merge "msm: ipa: Fix ipa3_wwan_xmit return type" 2020-03-01 18:13:00 -08:00
qctecmdr
36bcbe78a2 Merge "mmc: sdhci-msm: Support Retention of SDCC Regs in CX Collapse" 2020-03-01 18:13:00 -08:00
qctecmdr
2e946461cd Merge "msm: kgsl: Override UBWC configuration for A660 based on DDR type" 2020-03-01 18:13:00 -08:00
qctecmdr
4367382eb6 Merge "mm/oom-kill: Remove obsolete IS_ENABLED check" 2020-03-01 15:21:59 -08:00
Gwan-gyeong Mun
043874de92 drm: Add DisplayPort colorspace property creation function
Because between HDMI and DP have different colorspaces, it adds
drm_mode_create_dp_colorspace_property() function for creating of DP
colorspace property.

v3: Addressed review comments from Ville
    - Add new colorimetry options for DP 1.4a spec.
    - Separate set of colorimetry enum values for DP.
v4: Add additional comments to struct drm_prop_enum_list.
    Polishing an enum string of struct drm_prop_enum_list
v5: Change definitions of DRM_MODE_COLORIMETRYs to follow HDMI prefix and
    DP abbreviations.
    Add missed variables on dp_colorspaces.
    Fix typo. [Uma]
v6: Addressed review comments from Ilia and Ville
   - Split drm_mode_create_colorspace_property() to DP and HDMI connector.
v7: Fix typo [Jani Saarinen]
    Fix white space.
v8: Addressed review comments from Ville
   - Drop colorimetries which have another way to distinguish or which
     would not be used.
v9: Addressed review comments from Ville
   - Split hunk into renaming and adding of code.

Change-Id: I7fa6831aeca1ae2e8dca79bad4f1dec373b53199
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-5-gwan-gyeong.mun@intel.com
Git-commit: 45cf0e91df8c75c3a0c69e54d01cf42e24af365b
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2020-02-28 17:02:44 -08:00